1. Field of the Invention
The present invention relates to a technology for calculating power consumption of a circuit.
2. Description of the Related Art
Recently, semiconductor integrated circuits (IC) are becoming to have high-density, large-scale, and high processing speed. Along with such progress, power consumption of the semiconductor IC has increased. To decrease the power consumption, it is necessary to precisely calculate power consumption of a semiconductor IC to design the semiconductor IC.
A method of calculating power consumption of a semiconductor IC has been proposed in, for example, Japanese Patent Laid-open Publication No. 2001-265847. According to the method, a power consumption calculating apparatus, by simulating a semiconductor IC, searches a node and an output terminal in the semiconductor IC of which logic values are unknown. The apparatus uniquely defines a signal level for the node and the output terminal based on the real semiconductor IC. Thus, the apparatus estimates power consumption of the semiconductor IC. However, with a conventional power consumption calculating technique, it is difficult to precisely calculate the power consumption at the designing stage. For example, power consumption of a semiconductor IC depends on data input into the semiconductor IC. The conventional apparatus calculates the power consumption while the semiconductor IC performs various operations, and therefore, the calculated power consumption is overestimated. Therefore, burden on a designer and a design period increase.
According to the power consumption calculating apparatus disclosed in Japanese Patent Laid-open Publication No. 2001-265847, the apparatus can not precisely calculate power consumption because the apparatus uniquely defines a signal level for the node and the output terminal having unknown logic value. Therefore, burden on a designer and a design period increase.